1. Field of the Invention
The present embodiments relate to a method for improving a yield of semiconductor integrated circuits (ICs). More particularly, the present embodiments relate to a method for improving a yield of a semiconductor IC by adding a margin to a metal pattern, a poly (polysilicon) pattern, or an active pattern of a layout of the semiconductor IC, and a recording medium having the method recorded thereon.
2. Description of the Related Art
A semiconductor layout may be designed based on rules associated with each of multiple patterns. Each of the rules may play an important role in arranging the corresponding pattern within a semiconductor layout.
Each of the rules may be based on a ground rule (GR) measured in a manufacturing part. The GR is also referred to as a minimum rule, and may correspond to a minimum value of each of rules associated with a metal pattern, a poly pattern, and an active pattern.
When a computer or a user designs a pattern within a layout of a semiconductor IC, if a value, e.g., a pattern width, of the rule associated with the pattern is designed to be smaller than the value of the GR, a defective semiconductor IC may be generated.
With current developments in semiconductor IC layout technology, a design of multiple patterns may be conducted with associated rules having values of sub-microns or less, and thus it may be difficult to obtain a satisfactory yield by only using the GR.
A recommended rule (RR) obtained by adding a predetermined margin to the GR may thus be proposed. When the RR is applied to the values of rules associated with patterns, the layout of the semiconductor IC may provide a better yield. The RR may allow the fail rate of a layout to be “0”, so that when the RR is applied to each of the rules, the yield of the layout may be maximized.
However, when the RR is applied to each of the rules, the size of the layout may increase. When the values of the rules in the layout having a predetermined size are greater than the values of the RR, it may be difficult to integrate the patterns into the semiconductor IC.
A method for improving the yield of semiconductor ICs may divide a layout pattern designing rule into the GR and the RR, and then design patterns of a layout so as to satisfy the RR. A processor or a user may calculate a percentage of patterns that satisfy the RR within all patterns within the layout, and may also calculate a threshold value that is a minimum percentage of times the RR may be satisfied with the patterns. When a percentage of occasions when the RR was satisfied is greater than or equal to the threshold value, the processor or user may determine the corresponding patterns to have passed, and the layout may be designed with these patterns. When the percentage of occasions the RR was satisfied is less than the threshold value, the processor or user may determine the corresponding patterns to have failed, and the patterns may be corrected so as to satisfy the RR. However, the rule associated with the pattern is divided into the GR and the RR, and it may be difficult to apply the RR to a rule having a large difference between the GR value and the RR value because the fixed size of the layout.
In addition, the processor or user may have difficulty in setting a standard for determining the threshold value, and when a percentage of patterns that satisfy the RR is less than the threshold value, the patterns may not be able to be corrected because the space of the layout may be insufficient.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention, and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.